Current communication tools can quickly and easily survey any information over the world. Such a convenient situation was realized following the well-known semiconductor device trend, that is, the increasing wafer size and the shrinking design rule. The silicon wafer size increased from several mm to 300 mm; the integrated circuit design rule shrunk from μm-order to nm-order. It should be noted that the trend was caused by an economy, not by a scientific interest.
The smaller the design rule, the larger the device production volume from the fixed-size wafer. This model significantly helps an economy.
An additional model is that the process rate, such as diffusion rate, deposition rate, etc, remains the same over various wafer sizes.
For example, the chemical vapor deposition rate is described as functions of concentration, temperature, etc, but not a function of wafer size. The larger wafer is thus expected to produce more device chips for the same duration as that using the smaller wafer.
Unfortunately, the production rate model does not work because of process engineering reasons.
The duration for the heating, gas supplying and mixing operations becomes long with the increasing wafer size. On the other hand, too small wafer is not easy to be handled and processed. Additionally, the current electronics industry flexibly produces various kinds of devices with various lots, small to huge.
From an economic standpoint, preferring a suitable wafer size is reasonable, such as half-inch for the minimal Fab system.
The Minimal Fab system has been researched and developed by the National Institute of Advanced Industrial Science and Technology (AIST) and the Fab System Research Consortium. The Minimal Fab Promoting Organization is working with them as the major force. To accelerate the realization of the Minimal Fab industry, more researchers, engineers and companies are welcome.